July 18, 2003
AMD PRICING WILL DROP, RAM HEADED THE OTHER WAY
AMD will have their regularly scheduled price drop at the end of this month. As usual we will not see a drastic price drop on the low end side. It will be mostly on the cutting edge processors, Barton core Athlon XP’s, Athlon MP’s & Opteron. We should see the release of the Athlon 64, also known as the Clawhammer, around September. A few of the low end processors will also reach end of life. Say goodbye to the 2000 MP for sure. We should see 2000 XP and probably 2200 XP go away as well. Progress never ends.
The Athlon 64 will probably be seen first in a 940 pin layout but it will be quickly followed by a 939 pin layout. We will then see a more reasonable version of the chip with 512K cache in a 754 pin design. Designations for these chips will start with a 3100+ to 3400+. They will crank it up to 3700+ by the end of the year. Originally, cache on these chips is expected to be 1MB. However, when the 3700+ is released, expect to see the 3100+ change to a 256K cache. Cache memory is expensive to produce and more expensive to make it small. The Barton core, AMD’s latest XP endeavor was released with 512K cache. All previous XP chips had 256K. Consequently the Barton chip is larger. Chip makers continually try to make things smaller. It is difficult to do that with Cache memory. Pricing for the new releases has been announced. We just have to be patient.
I won’t say much about RAM as I have beaten it into the ground over the past few weeks. Simply said, there is unrest in this part of the industry and all the turmoil will continue. It will cause the price of RAM to increase steadily until there is resolution. We have been able to hold steady thanks to planning ahead and stocking up. However, our stock is turning and we will be affected within the next 1 to 2 weeks.
AMD THORTON
OK, it’s AMD Day at S&K. No, AMD is not moving to the North Denver Metro Area. (Wrong spelling anyway) This is the latest design change for the next generation of AMD XP processors. Now I am going to express my opinion so some of you may want to stop reading right here. This new design sucks! AMD will continue to crank up the clock speed but they are going to “disable” half of the cache on the chip. It will be made on the same platform as the Barton. This will help streamline the manufacturing process. What’s up with disabling cache? It sounds kind of stupid to me. Let’s weigh the pros and cons.
Pro – In the manufacturing process there are always a certain number of chips that are discarded due to defects. This is obviously costly. With the ability to manufacture the Barton processor and the Thorton processor on the same platform, fewer chips are discarded. If the defect is in the cache, they have the ability to map around the bad cache disabling it and calling it Thorton. Considering the current economic crunch felt by all manufacturers this would certainly help reduce overall cost in production.
In my early days of this industry I was distributing memory from Micron that was somewhat unusual. These were 32MB 72 pin SIMMS with 12 chips, 6 on each side. Those with the understanding of RAM manufacturing, bits, and bytes, knew this was an unusual design. Most did not question it because the success rate of this RAM was phenomenal. The RMA rate was one of the lowest I had ever seen. This RAM design sheds light on the Thorton design. The DRAM chips on this memory were known defective. After testing by Micron they were moved off as seconds and assemblers would use them but map around the bad sections. Normal 32MB SIMMS had 8 chips on a single side. The assemblers could map around 1/3rd of each DRAM chip only using the known good parts, hence, 12 chips at 2/3rds per chip equals the same as 8 good chips. This is a great way to make use of otherwise useless silicon.
Con – What’s up with selling known defective CPU’s? Enough said.
There is still some speculation whether or not AMD will follow through with this program.
S&K